1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device including a sense amplifier.
2. Description of the Related Art
In general, semiconductor memory devices including the double data rate synchronous DRAM (DDR SDRAM) have a large number of memory cells therein. With the rapid increase in integration density of semiconductor memory devices, the number of memory cells included in semiconductor memory devices has also increased. The memory cells in a memory device are arranged regularly in one or more memory cell arrays, which are also commonly referred to as memory cell mats.
The memory cell structure of a semiconductor memory device may be roughly divided into a folded bit line architecture and an open bit line architecture.
The open bit line architecture includes a driving bit line for driving data and a reference bit line, which are arranged in different memory cell mats, with reference to a bit line sense amplifier arranged in a core region of the semiconductor memory device. Noise generated from the driving bit line is different from noise generated from the reference bit line, and do not offset each other. Thus the open bit line architecture is subject to bit line generated noise.
In the folded bit line architecture, a unit memory cell is designed to have an 8F2 structure, whereas in the open bit line architecture, a unit memory cell is designed to have a 6F2 structure. The unit memory cell structure determines the size of a semiconductor memory device. For the same data storage capacity, a semiconductor memory device having the open bit line architecture may be designed to have a smaller size than a semiconductor memory device having the folded bit line architecture.
FIG. 1 is a circuit diagram of a semiconductor memory device with a general open bit line architecture.
Referring to FIG. 1, each of first and second memory cell mats 210 and 220 in the semiconductor memory device with the open bit line architecture includes a plurality of memory cells for storing data. Each of first and second memory cell mats 210 and 220 may include a plurality of memory cell mats stacked on top of each other in a three dimensional configuration (not shown). The first memory cell mat 210 includes a first bit line BLT1 arranged therein, and the second memory cell mat 220 includes a first bit line bar BLB1 arranged therein.
A sense amplifier unit 230 serves to sense and amplify the voltages of the first bit line and bit line bar BLT1 and BLB1. The sense amplifier unit 230 senses and amplifies the voltages of the first bit line and bit line bar BLT1 and BLB1 according to first and second bit line isolation signals BISH and BISL. The sense amplifier unit 230 includes transistors which are turned on in response to the first and second bit line isolation signals BISH and BISL, and a latch-type sense amplifier circuit configured to perform a sense amplification operation. The sense amplifier circuit of the sense amplifier unit 230 senses the data transmitted through the first bit line and bit line bar BLT1 and BLB1, and amplifies the data to a voltage corresponding to a pull-up supply voltage RTO or pull-down supply voltage SB which is applied as power to the sense amplifier circuit all of which are well known in the art and thus are not illustrated in detail herein.
As described above, the open bit line architecture includes the driving bit line and the reference bit line arranged in different memory cell mats. For example, when data are driven to the first bit line BLT1, the first bit line bar BLB1 arranged in the second memory cell mat 220 becomes the reference bit line, and when data are driven to the first bit line bar BLB1, the first bit line BLT1 arranged in the first memory cell mat 210 becomes the reference bit line.
Thus, the open bit line architecture does not require separate transistors for separately operating the sense amplifier unit 230 for the first memory cell mat 210 and the second memory cell mat 220, respectively, and the sense amplifier unit 230 has only to sense and amplify the voltages of the first bit line BLT1 and the first bit line bar BLB1 according to the activated word line WL.
FIG. 2 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 2, the semiconductor memory device includes a command and address receiver 310, a bank address and command decoder 320, an address register 330, a row address decoder 340, a mat selection unit 350, a row decoder and mat controller 360, a word line decoder 370, and a DRAM core 380, which are well-known to those skilled in the art.
The DRAM core 380 includes a plurality of DRAM array units each having DRAM memory cells and bit line sense amplifiers BLSA for amplifying data stored in the cells. The DRAM core 380 has the general open bit line architecture as described with reference to FIG. 1.
The row decoder 360 and a column decoder (not illustrated) locate a memory cell to be accessed in response to a command and address applied from a device external to the memory device. The command for a DRAM operation includes a row address and column address, for example, a Row Address Strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal.
The row decoder and mat controller 360 decode a row address RA<0:n> of the corresponding mat in response to the row address RA<0:n> which is generated by the row address decoder 340 as the RAS signal is enabled, a bank active signal ACT_BK<i> which is generated by the bank address and command decoder 320, and a mat select signal MATSEL<0:k> which is generated by the mat selection unit 350.
The word line decoder 370 generates a main word line select signal MWLB and a sub word line select signal FXB in response to the mat select signal MATSEL<0:k> and the decoded row address generated by the row address and mat controller 360.
When a word line WLB<i> in any one mat is activated during a read operation, enable signals SAEN<i> and SAEN<i+1> for the bit line sense amplifiers arranged at the top and bottom of the corresponding word line WLB<i> is enabled for sensing and amplifying data of a bit line which is coupled to a memory cell coupled to the word line WLB<i>.
FIG. 3 is a circuit diagram illustrating a part of the DRAM core 380 illustrated in FIG. 2.
Referring to FIGS. 2 and 3, the DRAM core includes a plurality of mats 410A to 410C, a plurality of sense amplifier arrays 420A to 420D, and sub word line drivers SWL DRV arranged at the left and right sides of each of the mats 410A to 410C.
Each of the sense amplifier arrays 420A to 420D senses and amplifies a bit line and a bit line bar (not illustrated) which are arranged in different mats. With reference to each of the sense amplifier arrays 420A to 420C, a bit line arranged in the upper mat is defined as an upper bit line BLU, and a bit line arranged in the lower mat is defined as a lower bit line BLD. When one word line of any one mat among the plurality of mats 410A to 410C is activated, all memory cells (not illustrated) coupled to the activated word line are opened. Then, bit lines BLU/BLD coupled to the memory cells share data, and all sense amplifiers within the sense amplifier arrays arranged at the top and bottom of the corresponding mat are enabled to perform a sense amplifying operation.
For example, when a word line WLB<i> of the second mat 410B is activated, the second and third sense amplifier arrays 420B and 420C arranged adjacent to the second mat 410B be activated to sense and amplify data of the corresponding bit lines. The second sense amplifier array 420B is activated in response to an (i+1)th sense amplifier enable signal, and the third sense amplifier array 420C is activated in response to an i-th sense amplifier enable signal.
Hereafter, a data sensing operation to the DRAM core 380 will be described with reference to FIG. 4. FIG. 4 is a timing diagram illustrating a data sensing operation to the DRAM core 380 of FIG. 3. Hereafter, referring to FIGS. 3 and 4, a sensing operation in case where a word line WLB<i> of the second mat 410B is activated will be described.
In the following descriptions, one sense amplifier included in each of the second and third sense amplifier arrays is taken as a representative example. With reference to the first sense amplifier 420B_1 of the second sense amplifier array 420B, a bit line arranged in the upper mat, for example, the first mat 410A is defined as the upper bit line BLU, and a bit line arranged in the lower mat, for example, the second mat 410B is defined as the lower bit line BLD.
The upper bit line BLU is amplified to a low level L while retaining a precharge voltage VBLP, and the lower bit line BLD shares high-level data information stored in a memory cell (not illustrated) with the upper bit line BLU as the word line WLB<i> is activated to the low level L. Then, the lower bit line BLB is sensed and amplified to the precharge voltage VBLP by the first sense amplifier 420B_1 of the second sense amplifier array 420B, and then amplified to the high level H while retaining the precharge voltage VBLP.
Furthermore, with reference to the first sense amplifier 420C_1 of the third sense amplifier array 420C, a bit line arranged in the upper mat, for example, the second mat 410B is defined as the upper bit line BLU, and a bit line arranged in the lower mat, for example, the third mat 410C is defined as the lower bit line BLD.
The upper bit line BLU shares high-level data information stored in a memory cell (not illustrated) with the lower bit line BLD, as the word line WLB<i> is activated to the low level L. Then, the upper bit line BLU is sensed and amplified to the precharge voltage VBLP by the first sense amplifier 420B_1 of the second sense amplifier array 420B, and then amplified to the high level H while retaining the precharge voltage VBLP. The lower bit line BLD is amplified to the low level L while retaining the precharge voltage VBLP.
Since the conventional semiconductor memory device with the open bit line architecture is configured in such a manner that one bit line is driven by one sense amplifier, the conventional semiconductor memory device cannot change the develop speed at which noise is caused.